Many semiconductor devices, such as memory devices, utilize both n-type field effect transistors (nFETs) and p-type field effect transistors (pFETs). One example of a memory device that uses both nFETs and pFETs is a static random access memory (SRAM) device. A typical SRAM device includes arrays of thousands of SRAM cells. Each SRAM cell may have four or six transistors (for example). A commonly used SRAM cell is a six-transistor (6T) SRAM cell. A 6T SRAM cell has two pFETs interconnected with four nFETs.
As technology progresses, the size of individual components and portions of semiconductor devices are continually being scaled down. This increases device speeds and allows for smaller integrated circuit chips to be produced. It also allows for more devices and even multiple systems to be placed on each chip. In turn, this allows consumer products and other equipment to be made smaller, lighter, and yet more powerful than previous products. It also allows for more features and functionality to be included in a single product (e.g., cell phones with cameras and massive storage for information, music, images, and videos).
SiGe has been known as a very promising material for scaled down CMOS technology. Embedded SiGe has been successfully integrated in source/drain regions of transistors as stressors to enhance the performance of devices, the devices based on such concept has been mass-productive. However, integrating more stressor components together such as Stress Memory Technology (SMT) for nFETs and Dual Stress Liners (DSL) for both pFETs and nFETs have been challenging. Hence, there is a need to find new ways to incorporate SiGe into transistor structures, while also reducing the complexity of manufacturing processes to improve or maintain manufacturing efficiency, device reliability, and production yield.